This standard defines a mechanism for the test of core designs within a system on chip (SoC). This mechanism constitutes a hardware architecture and leverages the core test language (CTL) to facilitate communication between core designers and core integrators.
IEEE 1500-2005 history
1970IEEE 1500-2022 IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
2005IEEE 1500-2005 Standard Testability Method for Embedded Core-based Integrated Circuits IEEE Computer Society document