The secondparagraph of 2.3D.151 (1 0/92) contains the following text: The pattern may be generated in a twenty-stage shift register whose 17th and 20th stage outputs are added in a modulo-two addition stage, and the result is fed back to the input of the first stage. An output bit is forced to be a ONE whenever the previous 14 bits are all ZERO.
ITU-T O.151 FRENCH-1992 history
1992ITU-T O.151 FRENCH-1992 ERROR PERFORMANCE MEASURING EQUIPMENT OPERATING AT THE PRIMARY RATE AND ABOVE