This specification specifies the data representation format of integrated circuit IP core (Intellectual Property Core, hereinafter referred to as IP) to support the hardware design process from register transfer level (RTL, Register Transfer Level) design planning to final verification. This specification includes the following content: the format of the RTL source code and its performance model required for the IP hard core and IP soft core, and a summary of the design constraint requirements. This specification covers the data formats used in structural netlists and some physical data types related to hard IP. This specification also includes a set of guidelines to reduce the possibility of namespace conflicts between different IPs and between IPs and other system logic, as well as some principles for handling namespace conflicts when they occur. The "Application Area" of the data format in this specification is defined as the description of the creation, definition, exchange and integration of integrated circuit IP. The "Application Area" of the data format in this specification is defined as the description of the creation, definition, exchange and integration of integrated circuit IP.