This test plan is broken into three major sections for the testing of bus controllers Electrical@ Protocol and Noise tests. General:This validation test plan defines the test requirements for verifying that the design of bus controllers meets the requirements of MIL-STD-1553B@ "Digital Time Division Command/Response Multiplex Data Bus." Application: This is a general test plan for any first article@ prototype@ or engineering preproduction bus controller designed to meet the requirements of MIL-STD-1553B. These requirements shall apply to the bus controller under test@ when invoked in a specification or statement of work. This document deals only with bus controller functions that are explicitly described in MIL-STD-1553B. This document does not specify tests that check the integrity of data from the subsystem to the bus@ nor does it attempt to address the system test requirements.
SAE AS4113-1989 history
2017SAE AS4113A-2017 Validation Test Plan for the Digital Time Division Command/Response Multiplex Data Bus Bus Controllers
2011SAE AS4113-2011 VALIDATION TEST PLAN FOR THE DIGITAL TIME DIVISION COMMAND/RESPONSE MULTIPLEX DATA BUS BUS CONTROLLERS
1989SAE AS4113-1989 Validation Test Plan for the Digital Time Division Command/Response Multiplex Data Bus Bus Controllers