IPC TM-650 2.6.3.5-2004
Bare Board Cleanliness by Surface Insulation Resistance

Standard No.
IPC TM-650 2.6.3.5-2004
Release Date
2004
Published By
Institute of Interconnecting and Packaging Electronic Circuits (IPC)
Scope
This document describes manufacturing process simulations for use with applicable component specifications to assure that electronic components can meet expected reliability requirements after exposure to assembly factory processes. It is not intended as an assembly production specification or a stand-alone qualification document. The procedure consists of a set of assembly process simulations that can be performed by either the component user or manufacturer prior to reliability testing as specified in the applicable component qualification and reliability monitoring documents. The simulations include alternative conditions depending on the component type, physical characteristics and anticipated use. The levels defined can be used for describing either expected performance characteristics by the manufacturer or the required characteristics for the users assembly process.



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