JEDEC JESD33B-2004
Standard Method for Measuring and Using the Temperature Coefficient of Resistance to Determine the Temperature of a Metallization Line

Standard No.
JEDEC JESD33B-2004
Release Date
2004
Published By
(U.S.) Joint Electron Device Engineering Council Soild State Technology Association
Scope
This method is intended for determining the temperature coefficient of resistance (at a given temperature) of aluminum- and copper-based thin-film metallizations that are used in microelectronic circuits and devices. This method is intended for estimating a mean temperature of a metallization line stressed in an accelerated electromigration stress test before any irreversible change in resistivity occurs due to the current-density and temperature stresses imposed. This method is intended for using a metallization test line as an ambient-temperature sensor. It uses the predetermined values for the temperature coefficient of resistance of the metallization and the resistance of the test line at a reference temperature. This method is designed for use under conditions where the metallization resistivity is linearly dependent on temperature and where it does not suffer any irreversible changes. For aluminum metallizations, a linear dependence appears to hold until approximately 420 ºC, considerably above anticipated stress temperatures. For copper metallizations, a departure from a linear dependence becomes evident at temperatures as low as 200 °C. A correcting function is used for copper to correct for departures from linearity at these higher temperatures This method is applicable to metallization test lines with or without vias, and with oxide or low-k dielectrics. While the method is designed for use with aluminum- and copper-based metallizations, it may also be used with other metals and alloys for conditions that satisfy the linear dependence and stability stipulations in the previous paragraphs. The metallization structure used in the method may be measured while on a wafer or a part therefrom, or as part of a test chip bonded to a package and electrically accessible via package terminals.



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